The present invention relates to a processor for a digital echo canceller, and in particular to such a processor which generates an echo estimate of an actual echo on an echo path.
Long distance telephone facilitates usually comprise four-wire transmission circuits between switching offices in different local exchange areas, and two-wire circuits within each area connecting individual subscribers with the switching office. A call between subscribers in different exchange areas is carried over a two-wire circuit in each of the areas and a four-wire circuit between the areas, with conversion of speech energy between the two and four-wire circuits being effected by hybrid circuits. Ideally, the hybrid circuit input ports perfectly match the impedances of the two and four-wire circuits, and its balance network impedance perfectly matches the impedance of the two-wire circuit, so that signals transmitted from one exchange area to the other will not be reflected or returned to the one area as echo. Unfortunately, due to impedance differences which inherently exist between different two and four-wire circuits, and because impedances must be matched at each frequency in the voice band, it is virtually impossible for a given hybrid circuit to perfectly match the impedances of any particular two and four-wire transmission circuit. Echo is, therefore, characteristically part of a long distance telephone system.
Although undesirable, echo is tolerable in a telephone system so long as the time delay in the echo path is relatively short, for example shorter than 40 milliseconds. However, longer echo delays can be distracting or utterly confusing to a far end speaker, and to reduce the same to a tolerable level an echo canceller may be used toward each end of the path to cancel echo which otherwise would return to the far end speaker. As is known, echo cancellers monitor the signals on the receive channel of a four-wire circuit and generate estimates of the actual echoes expected to return over the transmit channel. The echo estimates are then applied to a subtractor circuit in the transmit channel to remove or at least reduce the actual echo.
In simplest form, generation of an echo estimate comprises obtaining individual samples of the signal on the receive channel, multiplying each sample by the impulse response of the system and then subtracting, at the appropriate time, the resulting products or echo estimates from the actual echo on the transmit channel. As is known, in actual practice generation of an echo estimate is not nearly so straightforward.
Transmission circuits, except those which are purely resistive, exhibit an impulse response which reflects signal frequency and amplitude dispersive characteristics, since phase shift and amplitude attenuation vary with frequency. To this end, a suitable known technique for generating an echo estimate contemplates manipulating representations of a plurality of samples of signals which cause the echo and samples of impulse responses of the system through a convolution process to obtain an echo estimate which reasonably represents the actual echo expected on the echo path. In performing the convolution process with digital echo cancellers, to reduce the complexity and increase the speed of operation and capacity of the circuitry it has been found desirable to encode the signal and impulse response samples in digital A-law format, which is a companding function. For example, an A-law format having an 8-bit output is equivalent to a 12-bit linear code in resolution and has a dynamic encoding range of 62 dB. Such an encoding format is also particularly useful in such applications because of its compatibility with 8-bit microprocessors commonly found in digital echo cancellers.
A unique characteristic of the A-law format is its similarity to binary logarithms. Because of this characteristic, previous approaches to the multiplication of two A-law factors with non-zero exponents have contemplated a direct addition of the two pseudo-logarithmic quantities. Unfortunately, the products of the largest factors, which contribute most to the sum of the products accumulated by the convolution process, contain the largest errors, and although an error correction term is subsequently estimated and added to the result to compensate for the product approximation obtained by the addition of two pseudo-logarithmic quantities, every "multiplication" involving non-zero exponents is nevertheless imprecise. In addition, a typical digital filter or echo cancelling application accomplished by means of a convolution process may require as many as 256 accumulated products, each of which is an approximation as a result of pseudo-logarithmic addition, so that the resulting accumulation may contain as many as 256 "summing" errors prior to any truncation or round-off. In a system such as an adaptive echo canceller where the accumulated product may be used to modify one set of multiplier inputs, decreased stability as well as imprecision results. Consequently, a technique is required for accurate multiplication and accumulation of pairs of A-law factors in order to achieve an acceptable digital filtering process for such applications as echo cancelling and speech synthesizing.